A CMOS/SOI Continuous-Time Low-Pass gm-C Filter

This paper describes a preliminary comparative analysis between continuous-time gm-C filters based on a specific transcondutor but designed according to CMOS/bulk (conventional) and CMOS/SOI fabrication processes. A compensation technique to minimize the phase-error (lead-phase) of the basic integrator owing to the relatively high output-conductance of the adopted transconductor is examined. Such a technique consists of moving the RHP zero frequency closer to the non-dominant LHP pole by adding an extra capacitance along the signal feedforward path. A 3rd-order low-pass, ladder-type elliptic-filter was designed and integrated on a 2μm CMOS/SOI fabrication process. At nominal bias and VDD=5V, the filter experimental parameters are fp=4.1MHz, fs=12MHz, Amax<2.47dB and Amin>39dB. As no meaningful gain-peaking around the roll-off frequency was found, small phase-error associated with basic integrators can be assumed. The filter linearity is described by a THD of 0.25% for a differential output voltage Vout=200mVpp.